1. Field of the Invention
The present invention relates to a differential logic circuit, and more particularly to a charge-redistribution low-swing differential logic circuit.
2. Description of the Related Art
For a current logic system, especially in design for a complicated high-speed circuit, a differential logic circuit is adopted in order to achieve both true signal and its complementary signal. For example, as shown in FIG. 1, in U.S. Pat. No. 4,570,084, this logic system comprises logic networks 10 and 12 each acting as a switch so that when logic network 10 is closed, logic network 12 is open. Input signal INPUTS and its complementary signal COMPLEMENTARY INPUTS are applied to logic networks 10 and 12, respectively, for controlling its switching operation in networks 10 and 12. Network 10 is connected between an output node 14 and a NMOS pull down transistor 16 connected to ground. Network 12 is connected between an output node 18 and a NMOS pull down transistor 20 connected to ground. A clock pulse .phi..sub.c is applied to the control of whether or not the transistors 16 and 20 are active.
A load circuit 22 comprises PMOS transistors 24 and 26 connected between a source of potential Vdd and output node 14, and PMOS transistors 28 and 30 connected between source Vdd and output node 18. An inverter 32 is connected between an output Q and output node 14. An inverter 34 is connected between a complementary output terminal Q of terminal Q and output node 18. Also, clock.phi..sub.c is applied to the control of whether or not the transistors 24 and 28 are active.
In the operation of precharging and equalizing, clock.phi..sub.c is at a potential level of logic 0. This turns off NMOS transistors 16 and 20 and turns on PMOS transistors 24 and 28. Therefore output node 14 and 18 are precharged to source Vdd. At this time, both output terminals Q and Q are at logic 0 level through corresponding inverters 32 and 34. As a result, PMOS transistors 26 and 30 are turned on in order to maintain the conductive state.
In the operation of evaluating the information provided by the complementary input signals INPUTS and COMPLEMENTARY INPUTS of its associated logic networks 10 and 12, clock.phi..sub.c is at a potential level of logic 1. This turns on NMOS transistors 16 and 20 and turns off PMOS transistors 24 and 28. Because network 10 is closed, output node 14 is effectively grounded. Because network 12 is open, output node 18 is prevented from discharging so as to maintain at logic 1 level. At this time, output terminal Q is at logic 1 level through inverter 32 and output terminal Q is at logic 0 level through inverter 34. As a result, PMOS transistor 26 is maintained in an off condition, and PMOS transistor 30 is maintained in an on condition.
In the foregoing conventional art, the complementary output signal pair are obtained by the differential logic circuit at the same time; additionally, its full swing is from source Vdd to ground Vss.
In current SRAM or DRAM applications, a sense amplifier is often used to detect and amplify an input signal pair; for example an input signal pair from a bit line and its complementary bit line, which have a slight voltage difference, such as a difference of about 100 mV.
Hereinafter, the schematic diagrams of FIG. 2 through FIG. 6 are used to depict the corresponding prior art applications.
Referring to FIG. 2A, as described in U.S. Pat. No. 4,843,264, a sense amplifier is used to rapidly amplify the difference between input signal IN and its complementary input signal INB. In the configuration of FIG. 2A, input signal pair IN and INB are coupled to two NMOS sensing transistors M5 and M6. A latch is formed by two cross coupled CMOS inverters M1-M3 and M2-M4, wherein a common gate input G1 of M2 and M4 are coupled to node n1, which is formed by the source-drain series connection of M1 and M3, thereby providing a complementary output signal OUTB. Likewise, a common gate input G2 of M1 and M3 are coupled to node n2 which is formed by the source-drain series connection of M2 and M4, thereby providing an output signal OUT. Nodes n3 and n4 couple the sources of the NMOS pull down transistors M3 and M4 to the drains of the NMOS sensing transistors M5 and M6, respectively. Pull down transistor M7 is activated when sensing is to be performed.
Referring to FIG. 2B, a sense amplifier combining with precharging and equalizing circuitry is illustrated. During precharging, since PMOS transistors M13, M14, and M17 constitute a precharge circuit and equalizing signal EQB is at logic 0 level, transistors M13, M14, and M17 are turned on, which will consequently activate nodes n1, n2 being precharged by equalizing signal EQB to Vdd and so equalized. Likewise, PMOS transistors M18, M19, and M20 also constitute a precharge circuit, therefore nodes n3, n4 are precharged by equalizing signal EQB to Vdd and so equalized. Further, during sensing, equalizing signal EQB is at logic 1 level, which will consequently disable two precharge circuits, then transistor M7 is turned on by control signal SE to pull down the potential on node n5. Assume that the voltage on signal IN is 100 mV higher than the voltage on signal INB, thereby producing a current difference between transistor M5 and transistor M6. The gate-to-source voltage of transistor M5 is higher than that of transistor M6. As a result, when sensing begins, node n3 will begin pulling down sooner than n4, and thus node n1 will be pulled down faster than n2. Therefore, the potential on node 4 is higher compared to node 3, and the potential on node 1 is lower compared to node 2. Thus, transistor M4 is less conductive than transistor M3 because the gate-to-source voltage on M4 (not shown in figure) will be decreased relative to the gate-to-source voltage on M3. The voltage on node n2 will quickly rise back towards Vdd (OUT) with transistor M4 beginning to shut down. Finally, the relatively high voltage on node n2 will keep transistor M1 off reinforcing the rate at which node n1 is pulled down to Vss (OUTB).
Accordingly, only a small voltage difference is required for detecting an input signal pair. For example, as the voltage on signal IN is 100 mV higher than the voltage on signal INB, two cross coupled CMOS inverters M1-M3 and M2-M4, which form a latch, will rapidly amplify the signal differential between signal IN and INB, and to thereby latch the sensed voltages into nodes n1 and n2 as signals Vss and Vdd, where nodes n1 and n2 constitute a complementary signal pair labeled OUTB and OUT.
Moreover, because one of the two devices on each of the latch (two cross coupled CMOS inverters M1-M3 and M2-M4) will be off, either the pull up transistor (M1 or M2) or the pull down transistor (M3 or M4) will be off on each side of the latch. Thus, after the same amplifier has latched, it consumes no d.c. power. The foregoing techniques provide the advantages of low power consumption, high speed operation, and sense amplifier outputting full swing from power Vdd to ground Vss.
Referring to FIG. 3A, which is another sense amplifier 9 as described in U.S. Pat. No. 4,910,713. Comparing sense amplifier 9 of FIG. 3A to the one in FIG. 2A, the main difference of both is that two sensing transistors exchange the positions with two lower NMOS transistors of the latch.
An input signal pair 15,17 of a sense amplifier 9 are coupled to NMOS sensing transistors N4 and N5. A latch is formed by two cross-coupled CMOS inverters 11,13. Inverter 11 with a common gate input G1 comprises a PMOS pull up transistor P2 and a NMOS pull down transistor N1 both coupled in series by a NMOS sensing transistor N4. The common gate input G1 of inverter 11 is coupled to an output node 25, which is a series connection point of source-to-drain electrode of PMOS transistor P3 and NMOS transistor N5, thereby providing output signal 23. Likewise, inverter 13 with a common gate input G2 comprises a PMOS pull up transistor P3 and a NMOS pull down transistor N2 both coupled in series by a NMOS sensing transistor N5. The common gate input G2 of inverter 13 is coupled to a complementary output node 27 which is a series connection point of source-to-drain electrode of PMOS transistor P2 and NMOS transistor N4, thereby providing output signal 21.
In addition, inverters 11,13 are coupled respectively to source Vdd and ground Vss by the coupling transistors P1, P4, and N3. Two PMOS pull up transistors P2, P3 couple transistors P1, P4 in parallel, respectively. NMOS coupling transistor N3 is coupled between ground Vss and two inverters 11 and 13 in series. During sensing operations, the gates of all three of the coupling transistors P1, P4, and N3 are connected together and are strobed by a control signal AMP STROBE on the line 29, i.e., during non-sensing operation, a low potential of the signal AMP STROBE on the line 29 will deactivate or electrically isolate the latching pairs of two cross coupled CMOS inverters 11,13, whereas, during sensing operation, a high potential of the signal AMP STROBE on the line 29 will activate the latching pairs of two cross coupled CMOS inverters 11,13.
During sensing operation, when NMOS coupling transistor N3 is activated under a high potential of the signal AMP STROBE on the line 29 and is therefore to be pulled down to ground Vss, PMOS coupling transistors P1 and P4 are then simultaneously disabled making the sensing operation perform the same as the processes in FIG. 2A. Meanwhile, only the voltage difference of input signal pair 15,17 is amplified and appeared on the corresponding output nodes 25 and 27.
During non-sensing operation, when NMOS coupling transistor N3 is deactivated under a low potential of the signal AMP STROBE on the line 29, PMOS coupling transistors P1 and P4 are then simultaneously active. Therefore the output nodes 25 and 27 corresponding to the cross coupled CMOS inverters 11 and 13 are pulled up to source Vdd, and no Vdd-to-Vss path and drain current exist through the CMOS inverters 11 and 13, thereby avoiding power dissipation.
Referring to FIG. 3B, an alternate embodiment is illustrated. An input signal pair 15', 17' of a sense amplifier 9' are coupled to PMOS sensing transistors P11, P12. A latch is formed by two cross-coupled CMOS inverters 11' and 13' which are coupled to transistors P11 and P12, respectively. Inverter 11' with a common gate input G1' comprises a NMOS pull up transistor N16 and a PMOS pull down transistor P13. The common gate input G1' of inverter 11' is coupled to an output node 25', which is a series connection point of the source-to-drain electrode of NMOS transistor N17 and PMOS transistor P14 of inverter 13', thereby providing output signal 23'. Inverter 13' with a common gate input G2' comprises a NMOS pull up transistor N17 and a PMOS pull down transistor P14. The common gate input G2' of inverter 13' is coupled to an output node 27', which is a series connection point of the source-to-drain electrode of NMOS transistor N16 and PMOS transistor P13 of inverter 11', thereby providing complementary output signal 21'.
In addition, inverters 11', 13' are coupled respectively to source Vdd and ground Vss by the coupling transistors N15, N18, and P10. NMOS transistor N16 of inverter 11' and NMOS transistor N17 of inverter 13' are coupled to transistors N15 and N18 in parallel, respectively. PMOS coupling transistor P10 is coupled between source Vdd and two inverters 11' and 13' in series. During sensing operations, the gates of all three of the coupling transistors N15, N18, and P10 are connected together and are strobed by a control signal 31, i.e., during non-sensing operation, a high potential of the control signal 31 will deactivate or electrically isolate the latching pairs of two cross coupled CMOS inverters 11', 13', whereas, during sensing operation, a low potential of the control signal 31 will activate the latching pairs of two cross coupled CMOS inverters 11', 13'.
As noted above, during sensing operation, when PMOS coupling transistor P10 is activated under a low potential of the control signal 31 and is therefore to be pulled up to source Vdd, NMOS coupling transistors N15 and N18 are then simultaneously disabled making the sensing operation perform the same as the processes in FIG. 2A. Meanwhile, only the voltage difference of input signal pair 15,17 is amplified and sequentially appearing on the corresponding output nodes 25 and 27.
During non-sensing operation, when PMOS coupling transistor P10 is deactivated under a high potential of the control signal 31, NMOS coupling transistors N15 and N18 are then simultaneously active. Therefore the output nodes 25' and 27' corresponding to the cross coupled CMOS inverters 11' and 13' are pulled down to ground Vss, and no Vdd-to-Vss path and drain current exists through the CMOS inverters 11' and 13', thereby avoiding power dissipation.
In the conventional sensing operation as described above, when a pair of input signals are amplified up to full swing from the potential of power source to the potential of ground, the sensing amplifier will output the corresponding output pair of input signal pair. Therefore, when the delay time for pulling up from the potential of power source to the potential of ground is longer, this design will not work well for a high-speed device such as a memory. To improve the above, an alternate conventional technique is applied, wherein the sense amplifier will output the correspondingly resulting signal pair as soon as the input signal pair is amplified up to an acceptable level having a small difference between input signals.
Referring to FIGS. 4A and 4B, in the article in "IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 29, NO. 12. DECEMBER 1994" by Mastaka Matsui etc., there is disclosed an alternate sensing-amplifying technique. The sensing-amplifying technique combines NMOS dynamic differential logic network, for example, DPTL (differential pass transistor logic) or CPL (complementary pass transistor), with SA-FF (sense amplifying pipeline flip-flop circuit), wherein the basic concept of SA-FF is that a sense amplifier is merged into a latch which is synchronous to system clock CLK. SA-FF amplifies low-swing differential (.DELTA.Vin) inputs D, D. Here, Q, Q are the full-swing outputs of SA-FF. In this case, there is no need of additional inverter to generate a local clock with the opposite polarity because SA-FF can be operated in the control of a true single-phase clock.
In an operating manner, combinational logic mainly outputs the signals A, B to an NMOS differential logic network. Differential inputs D, D are generated from the NMOS differential logic network controlled by a .phi.p pulse. The differential inputs D, D are pre-discharged to ground while pulse .phi.p is active at logic 1 potential in a pre-discharging state. The foregoing outputs Q, Q of SA-FF latch the result last time while complementary system clock CLK is at logic 1 potential; pulse .phi.p is at logic 0 potential for evaluation of the logic network, therefore NMOS differential logic network has the outputs with a difference .DELTA.Vin (about 100 mV) from inputs D, D. At this time, as soon as clock CLK transits from logic 1 to the falling edge of logic 0, SA-FF is activated immediately without waiting for the difference .DELTA.Vin further developed and performs the sense-amplified and latch operation for inputs, thereby obtaining a complementary pair of differential outputs Q, Q. Alternately, during clock CLK remaining on logic 0 potential, the difference .DELTA.Vin is further developed. Because only NMOS logic is adopted, the full-swing of inputs D, D is the difference Vdd-Vtn between Vss-to-Vdd (not shown) and NMOS transistor threshold voltage Vtn (about 700 mV).
NMOS differential logic is mainly used in the circuit mentioned above. With the circuit of pre-discharging to ground during non-sensing, one of input signals D, D will be pulled up from ground to the difference Vdd-Vtn between source Vdd and NMOS transistor threshold voltage Vtn. Also, when the difference .DELTA.Vin of inputs D, D is a small value (about 100 mV), SA-FF is active immediately and performs the sense-amplified and latch operation, thereby obtaining a complementary output pair Q, Q. But, it is disadvantageous in a low-frequency device for one of inputs D, D to be pulled up continually from Vss to Vdd-Vtn when pulse .phi.p remains on logic 0 potential for a long time, thereby suffering from high power dissipation.
Referring to FIG. 5, in the article in "1998 Symposium on VLSI Circuits Digest of Technical Papers", there is disclosed a sense-amplifier SA combined with isolated transistors I1, I2, wherein the sense-amplifier SA comprises cross-coupled CMOS inverters M41, M42, M43, M44, and NMOS pull down transistor M45.
During non-sensing, bit line BL and its complementary bit lineBL is charged to source potential. Meanwhile, isolated signal ISO is at logic 0 potential, therefore isolated transistors I1, I2 are turned on, and nodes Al', A2' are charged to a source potential. During sensing, one of the complementary bit line pair BL, BL will be pulled down so that the voltage difference is developed to a constant difference such as 100 mV. Also, one of nodes A1', A2' will therefore be pulled down. Sequentially, isolated signal ISO is at logic 1 potential, therefore nodes A1', A2' are isolated due to isolated transistors I1, I2. The sense-amplifier is enabled after pull down transistor M45 is active under signal SET at logic 1 potential. As a result, the output terminal of NAND gate A1 on the side of the complementary bit line BL outputs a true signal, and the output terminal of NAND gate A2 on the side of the bit line BL outputs the true signal complement.
Namely, during sensing operation, one of the input signal pair will be pulled down to ground as mainly mentioned above. Then, input terminals BL, BL as soon as they have only a small difference such as 100 mV, are isolated by transistors I1, I2 and immediately sense-amplified and latched by the sense-amplifier, thereby obtaining a complementary differential output pair. However, it is disadvantageous when the power is continuously dissipated by pulling down one of input signal pair BL, BL from source to ground.
In addition, referring to 6A-6B, in the article in "IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 4. APRIL 1995" by Mitsuru Hiraki etc., there is disclosed a DDL bus (data-dependent logic bus) technique, which reduces its voltage swing using charge sharing between bus wires and an additional bus wire such as a dummy ground wire. First, according to a conventional n-bit bus of FIG. 6A, the voltage swing of bus signals coincides with the supply voltage Vdd. Thus, the bus power dissipation P required to switch n bits of the bus signals is given by: EQU P=n*f*Cw*V.sup.2 dd
where f and Cw are the switching frequency and wiring capacitance.
According to a n-bit bus signals of FIG. 6B, after adding a dummy ground bus wire (which is grounded at initial, then floated), the voltage swing of DDL bus wires based on n-bit charge sharing is reduced to Vdd/n+1, and the bus power dissipation required to switch the n-bit bus signals is reduced to P': EQU P'=[(n)/(n+1)]*f*Cw*V.sup.2 dd
In the foregoing conventional scheme, because each bit of the n-bit bus signals is different at logic 0 potential (for it is not the real ground potential), an alternate sense-amplifier is applied to sense and amplify the bus signals.